In current integrated circuits, the netlist is ever more complex. Consequently, there is an ever larger number of paths to be considered during the development of the circuit. The complexity of the netlist leads to long development lags.
Moreover, the analysis of the circuit is often not possible at the level of abstraction of the netlist. For example, the exploration of the design of the circuit on the basis of several constraints is always performed on the basis of Register Transfer Level, which is a higher level of abstraction where the circuit is simplified.
Now, when specific analyses of the circuit are performed (for example, during exploration to identify the best solution on the basis of one or more metrics, also dubbed criteria), it may not be necessary to examine all the paths of the netlist, a subset of paths may be sufficient to represent the analyzed behavior.
Also, the identification of a subset of paths representative of the behavior of the circuit is necessary when it is desired to monitor the operation of the circuit, given the impossibility of monitoring all the paths.
Within this framework, the technical problem addressed by the present invention relates to the reducing of the number of paths of the netlist to be considered for the analysis or the on-line monitoring of the circuit, i.e. the selecting of a subset of paths representative of the behavior of the circuit on the basis of several criteria defined by the circuit designer.
Little literature relating to the selection of the paths of a netlist exists. Most works do not consider the netlist of an integrated circuit, for example, several works deal with the selecting of the paths in a network. It is in particular possible to cite the article by N. G. Senarath, D. Yu, H. Zhang, I. Bahceci, P. Zhu, W. Tong, “Path selection for a wireless system with relays”, Patent No. US 2013/0010601 A.
When the netlist is considered, its simplification is often performed in terms of reduction of logic gates and not of paths: M. L. Case, J. R. Baumgartner, R. L. Kanzelman, H. Mony, “Logical circuit netlist reduction and model simplification using simulation results containing symbolic values”, U.S. Pat. No. 8,418,119 B2.
A solution to the problem of the selecting of the paths of a netlist which has nonetheless already been proposed describes the identification of a path which maximizes or minimizes a criterion. The most common and well known example relates to the identification of the critical path of an integrated circuit, where the path having the longest propagation time is identified. The problem posed by solutions of this type is that the list of paths is reduced to a single path. Also a single metric is taken into account for the selection of the path.
Some of the Applicant's previous works, in particular described in the references hereinafter: C. Bertolini, O. Heron, N. Ventroux, F. Marc, “Relation between HCl-induced performance degradation and applications in a RISC processor”, IEEE Int. On-Line Testing Symposium, 2012, pp. 67-72, 0. Heron, C. Bertolini, C. Sandionigi, N. Ventroux, F. Marc, On the simulation of HCl-induced variations of IC timings at high level“, Journal of Electronic Testing, 2013, Vol. 29, N. 2, pp. 127-141, and C. Sandionigi, O. Heron, C. Bertolini, R. David, When processors get old: Evaluation of BTI and HCl effects on performance and reliability”, IEEE Int. On-Line Testing Symposium, pages 185-186, July 2013, identify a path of the netlist on the basis of several criteria, while having a different aim from the selecting of the paths. The aim of these works is to analyze the temporal degradation of an integrated circuit. By considering the activity of the circuit and the lag of each path of the netlist (it being possible to consider these to be the two initial criteria), the works identify the path which is most sensitive to the degradation mechanisms. Solutions of this type do not make it possible to select a subset of paths representative of the behavior of the circuit so as to perform specific analyses.
In these articles, the aim sought is the evaluation of the temporal degradation of each path of the netlist so as to identify the most sensitive path. The criteria taken into account to characterize the netlist are the initial lag and the activity along the path. The method does not make it possible to define a strategy for selecting paths representative of the behavior of the circuit, which is the subject of the present invention. Consequently, the aim of accelerating the specific analyses or the on-line monitoring of the circuit cannot be achieved.